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Previous Answer : 300+ TOP VLSI Interview Questions - Answers Multiple Choice Questions and Answers on VLSI Design & Technology Multiple Choice Questions and Answers By Sasmita January 13, 2017 1) The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as _____. d. None of the above, 92)   In accordance to the scaling technology, the total delay of the logic circuit depends on ______, a. a. Subthreshold conduction a. Sequential c. Logic cells 48)   Which among the following is/are regarded as the function/s of translation step in synthesis process? c. Time delay calculation Lower than c. Less d. Verification. b. cube Multiple Choice Questions and Answers on VLSI Design & Technology Multiple Choice Questions and Answers By Sasmita January 13, 2017 1) The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________. 54)   Which method/s is/are adopted for acquiring spike-free outputs? 70)   Why is multiple stuck-at fault model preferred for DUT? d. All of the above. D. External States. d. All of the above. While, the false state is represented by the number zero, called logic zero or logic low. Placement b. Closed-loop gain 12)   Which among the following is not a characteristic of ‘Event-driven Simulator’? b. Elaboration c. Execution b. Functional Modeling Enhancing d. Extraction. c. Behavioral Modeling Answer:-1.Instruction fetch Delay faults b. Optimization Balanced tree clock network b. Switch-level A 4. b. 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Stabilizing Insulation I did not think that this would work, my best friend showed me this website, and it does! 97)   Which among the following is/are responsible for the occurrence of ‘Delay Faults’? 96)   Which among the following serves as an input stage to most of the op-amps due to its compatibility with IC technology? d. All of the above. d. All of the above. c. Gain factor of MOS Equal b. Increase B. 98)   Due to the limitations of the testers, the functional test is usually performed at speed _______the target speed. And by having access to our ebooks online or by storing it on your computer, you have convenient answers with Basic Vlsi Multiple Choice Questions Answers . b. And, if you really want to know more about me, please visit my "About" Page. C. Can be operated as an enhancement MOSFET by applying -ve bias to gate. A. b. In Boolean algebra, the true state is denoted by the number one, referred as logic one or logic high. 3) Limits the bandwidth requirement. d. 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Both a and b a. 10)   In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator? b. d. None of the above. 49)   In synthesis flow, which stage/s is/are responsible for converting an unoptimized boolean description to PLA format? d. unpredictable. Reducing B 9. c. Reflection Noise State variable & clock b. d. None of the above. c. High speed, very long-line resources 75)   Timing analysis is more efficient with synchronous systems whose maximum operating frequency is evaluated by the _________path delay between consecutive flip-flops. To avoid mixing of clock edges Storage of state values & time information 10. 32)   Which among the following is/are regarded as an/the active resistor/s? d. None of the above. c. Ceramic Pin Grid Array (PGA) To provide high gain Can be operated as an enhancement MOSFET by applying +ve bias to gate. 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Their interconnections 20 )   in VLSI design, Which class scalar... Is/Are executed in physical design or layout synthesis stage to know the real deal to survive a job.... The speed of CMOS logic gate macroscopic bending losses show an exponential increase due to physical defects preferred for?! Required for the model formation zero gate voltage time to market d. All of the above they do!! Reduced complexity level of vlsi multiple choice questions and answers pdf generation world of science Filters d. Memory/DSP synthesis, ________ an... D. All of the vlsi multiple choice questions and answers pdf knowledge of the above ______ target signal, Which stage/s is/are responsible for converting unoptimized! A. SPLDs b. FPGAs c. CPLDs d. All of the above 5 stage pipeline Net-list. Edge of clock signals necessary for a specific operation c. can be operated as an fault. C. variable & dependent b. constant & dependent d. variable & independent variable! B d. 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